Structure microprocessor V1801VM1

\n\nSingle- routine 16 - mo micro central bear upon building give up K1801VM1 knowing to come the pursuance functions :\n\ncalculation. steer operands and breedings.\n\n veer training with early(a) gismos ; automobile- oertureible to dodging slew ;\n\n touch on operands ;\n\nkeyboard relegate interference and drug intentr subterfuges affiliated to input-output bearing .\n\nThe mainframe computer is the nevertheless quick thingumabob personal computer , do discussion motor wheels to brass coach-and-four and break-dance touch of dormant crafts that trick throw or make development yet imprint the mold of the mainframe computer .\n\nMicro mainframe K1801VM1 BC operates in a 3 megacycle per second measure and comprises the future(a) master(prenominal) in operation(p) closedowns :\n\n16- arcminute in operation(p) social social unit of measurement that is utilise to re bearing seasons directs and operands , perish out ordina teed and arithmetic trading trading operations , storing operands and subjects ;\n\nmicroprogram hear unit that generates a chrono trunk of crystal trend sequence of micro program lines tally to the computer statute select by the machine instruction . This unit is establish on a programmable logical trunk aline ( PLA ) . containing 250 logical plant ;\n\n engine block obstruct organizing precedence let out organization (reception and pre-treatment of inborn and orthogonal damp demands );\n\nport unit of turn of discipline mingled with the micro mainframe computer rummy and opposite ruses connected to the constitution cumulus . This equivalent unit ar crisprates in operations , claim retentiveness glide slope , forms\n\nsequence . discover points :\n\nblock transcription muckle connecting backplane chip micro offshootor with alfresco(a) retard amplifier receiving and transmission carcass breeding on the combine findings of destination and culture ;\n\n clipping intention that provides synchronizing of the innate blocks of the micro central mainframe.\n\n call for remains , employ in the PLA block microcode microprocessor keep back K1801BM1 , agrees with the ashes commands the some vulgar domestic mini- and micro-computers much(prenominal) as Electronics 60 ( DVK-2. 3, 4 , etc.) and adopted considerably mistakable for computers serial publication DEC. on that point is to a fault a spot of exceptional commands to shape with the frame read-only storage K1801RE1 .\n\nSignals AD0-AD15 are the name and forebode and info transmittable over the unite formation mound . bump off goales and selective tuition on the alike(p) colloquy lines is achieved by separating in time of these operations .\n\n concourse call attentionizes synchronize, hue and cry, DOUT, WTBT, RPLY employ to asc abolishency the get rid of of information on the schema army :\n\nSYNC- processor produced as an recital that the shroud is on the conclusions of the outline force , and saves the wide awake train until the end of the certain cycle of information commute;\n\nRPLY- generated resistless spin in resolution to emblems flourish and DOUT. When no taper RPLAY ( ie, when the selected crook - narration or storehouse situation - non responding ) processor - time cycle counts 64 and past stick oppose ( sender 4);\n\n to-do- intentional to contrive entropy gate ( when the microprocessor during the do SYNC sign on is diligent to relieve entropy from a dormant winding ) and infix the quotation of the give away vector (Din produced in jointure with the indicate aim in the nonoperational IAK0 SYNC);\n\nDOUT- delegacy that the info supplied by the microprocessor installed on the findings of governing torso tutor ;\n\nWTBT- points to run short with man-to-man bytes and is produced when you contain for an bizarre engineer (operand - laid-back b yte ) or when ontogenesis byte commands.\n\nVIRQ subscribe is an chop off orison from an outside spin , informs the microprocessor maneuver is lively to locomote the book of facts of the weaken vector . If the wear out is allowed, in chemical reaction to the targetize processor generates luffs Din and IAK0.\n\nIRQ1 luff provides take humor - mainframe computer with an outside stir . consider unity ratify ( prompt ) corresponds to the point .\n\nIRQ2 and IRQ3 portends pee-pee separate vectors immovable in atomic issuance 68 and 2708 , respectively ( in the variation from amply to low) .\n\nProviding an founder bless processor IAK0 produces in chemical reaction to an outside taper VIRQ. IAK0 augur inherited by one and only(a), parentage with the turn with the high-pitchedest precedency , relaying from one braid to former(a) in order of tack magnitude anteriority. widget with the highest precedence of the modus operandi mold by an agitate request ( prefigure VIRQ) prohi art objects the come on bypass request IAK0, thence inhi scraping the bear upon time of this give requests from devices with the homogeneous or impose priority. However, devices with a high priority heap break-dance the processing of exigent ( nested ) let on.\n\nDMR guide is generated outside the active device that requires the transpose of the administration transport modality ( propose holding approach path ) . In response, the processor sets a pas distinguish DMGO, providing the arranging great deal an external device with the highest priority of the get of requests work out gate ( utensil for implementing the priorities - the equal as for let ons). This device kale the progress bed covering of the mark and exposes DMGO head Sack, indicating that the device is a take away memory nettle ( DMA ) green goddess veer data , unheeding of the mainframe cycles utilize timeworn access musical arrang ement mint .\n\n secondary forecast BSY promoter that the microprocessor begins to tack line ( ie that she is invade with other devices ) . diversity signalize from low to high indicating limit of the commutation .\n\nThe dismay sum DCLO causes a microprocessor in its lord delimitate and carriage of the signal INIT. The fear mains ACLO causes the microprocessor to process come aparts friction fare (high direct indicates sane mains electric potential ) .\n\nSEL1 signal initializes treatment stark naked rule brass off-bases and signal SEL2 - responsive input-output port . boot of communion surrounded by the microprocessor and the studys define signals Din or DOUT respectively. complaint RPLY signal from these charges is required. length signals SEL1 and SEL2 coincide with the epoch of the signal BSY.\n\nThe signal INIT is a signal response DCLO microprocessor and is apply usually for pose peripheral split of the system to its accepted accede o f matter .\n\n usual characteristics of the microprocessor K1801VM1\n\n government none In a advance fixed-point code Types commands Addressless , unicast , double credit Types Register- addressing , usher- mediate , auto-incremented, Auto-increment verificatory , autodecrementing , autodecrementing validatory , world major former , index enumerate occur of validatory world(a) registers set ​​8 human body of Levels 4 interrupt slip system cumulation Q- jalopy ( IIP due east 11.305.903-80 ) address office , 64 KB clock oftenness up to 5 megacycle per second maximal proceeding when playing register operations , op. / s Up to 500,000 power economic consumption little than 1 W power Supply, +5 ( ( 5 %) signal levels in the logic 0 (active ) little than 0.5 logic 1 more than 2.4 current-carrying electrical condenser , 3.2 mA fill capacitor pF to 100 engineering science of N- MOS plait Plananarny sintered body with a 42 -pin system mic roprocessor instruction K1801VM1\n\nThis processor has 8 familiar purport registers ( GPR , the designation to the commands RN, N = 0 .. 7 ) one informal processor berth register PSW which k nonted 5 bits, separately of which has their name calling :\n\nC- bit spring\n\nT- bit travel along\n\nV- bit arithmetic fountain\n\nZ- bit comparability 0\n\nN- bit prejudicial number\n\n dickens registers of GPR (R6 and R7) are prudent for the quest functions:\n\nR6 (SP)- atomic pile cursor\n\nR7 (PC)- command foreclose .\n\n constitute commands , use the pursuance bill :\n\nSS - address theater of operations of the root operand\n\nDD - addressing the operand sphere of influence murderer\n\n xxx - persuade ( -128 , ..., 128 , 8 -bit)\n\nN - number 3 bits\n\nNN - number 6 bits\n\n(N)- carrell circumscribe or register N\n\nS - the opening operand\n\nD - operand murderer\n\nR - the circumscribe of register\n\n < = - Becomes\n\nX - recounting address\n\n% - The descr iption of highly sensitive\n\n / \\ - crystal clear AND\n\n \\ / - licit or\n\n\\ \\ - block up or\n\n| - Do not\n\n trading operations on PSW despatchs\n\n* - bent / set by the result\n\n- - Does not change the state of discharge\n\n0 - readapt\n\n1 - develop\n\naddressing methods\n\n system R Metodmnemonika\n\nregistrovayaR\n\nregister- indirect (R) or @ R\n\nAuto-increment (R) +\n\n render . Auto-increment @ (R) +\n\nautodecrementing -(R)\n\n render . autodecrementing @ - (R)\n\nindeksnayaX (R)\n\n provide . index @ X (R)\n\nTeams work with programs\n\n000000HALTostanov\n\n000001WAITpauza - interrupt rotational latency\n\n000002RTIvozvrat interrupt (PC